\begin{table}[!htbp]

  \centering
  \begin{threeparttable}
  \caption{Simulation setup}\label{tab1}
  \Fsize{8}
  \renewcommand{\multirowsetup}{\centering}
    \begin{tabular}{cIl}
    
    \Xhline{1.1pt}
    Component & \makecell[c]{Configuration} \\
    \Xhline{1.1pt}
    Processor & 1 core, 1GHz, 2-width issue \\
    \hline
    L1 cache, nvSRAM & \tabincell{l}{32kB+32kB(I\&D) 4-way, 64B block, \\R/W latency: 1/1 cycle, \\ 1.714nJ/2kb store energy, \\ 1.06nJ/2kb restore energy~\cite{chiu2012low}} \\
    \hline
    L2 cache, STT-RAM & \tabincell{l}{1MB, 8-way, 64B line, \\R/W latency: 3/18cycle}  \\
    \hline
    ISA & ARMv7 \\
    \Xhline{1.1pt}
    
   
    \end{tabular}
     \end{threeparttable}
\end{table}